Cache memory and memory hierarchy
Computer Organization and Architecture · Engineering
CPU chip explorer
Interactive 3DLook inside a processor — data packets race between ALU, cache and control unit.
Controls
Drag the sliders or type a value — the simulation updates live.
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0.5×4×
Study notes
AMAT with L1 hit 1 cycle, miss rate 5%, miss penalty 100 cycles (to RAM): AMAT = 1 + 0.05x100 = 6 cycles. Halve the miss rate to 2.5% with a bigger cache: AMAT = 3.5 cycles, nearly twice as fast. This arithmetic justifies every cache transistor.