FPGA architecture basics
VLSI Design · Engineering
Study notes
Design: Verilog -> LUTs + routing; reprogram in seconds. Prototype ASIC; low-volume product. Slower/bigger than ASIC but no fab. Xilinx/Intel.
One notebook for every subject — open it anywhere.
VLSI Design · Engineering
Design: Verilog -> LUTs + routing; reprogram in seconds. Prototype ASIC; low-volume product. Slower/bigger than ASIC but no fab. Xilinx/Intel.